An Efficient Architecture of Forward Transforms and Quantization for H.264/AVC Codecs

Thanks to many novel coding tools, H.264/AVC has become the most efficient video compression standard providing much better performance than previous standards. However, this standard comes with an extraordinary computational complexity and a huge memory access requirement, which make the hardware architecture design much more difficult and costly, especially for realtime applications. In the framework of H.264 codec hardware architecture project, this paper presents an efficient architecture of Forward Transform and Quantization (FTQ) for H.264/AVC codecs in mobile applications. To reduce the hardware implementation overhead, the proposed design uses only one unified architecture of 1-D transform engine to perform all required transform processes, including discrete cosine transform and Walsh Hadamard transform. This design also enables to share the common parts among multipliers that have the same multiplicands. The performance of the design is taken into consideration and improved by using a fast architecture of the multiplier in the quantizer, the most critical component in the design. Experimental results show that our architecture can completely finish transform and quantization processes for a 4:2:0 macroblock in 228 clock cycles and the achieved throughput is 445Msamples/s at 250MHz operating frequency while the area overhead is very small, 147755μm2 (approximate 15KGates), with the 130nm TSMC CMOS technology

Factors Affecting Lecturer’s Commitment to Non-Public University: A Study in Ho Chi Minh City, Vietnam

By using SPSS 22.0 software to analyze the reliability through Cronbach’s alpha, EFA and AMOS 20.0 to modify the scale through CFA tool, test model through SEM, the study aimed to identify factors affecting lecture’s commitment to non-public university – a study in Ho Chi Minh city. Through  the offical survey with 510  samples,  the result showed the factors affecting lecture’s commitment including: satisfaction,  leadership and partnership.The satisfaction is the strongest factor. In other hand, the study identified that job satisfaction is affected by training, promotion, income.  Based on that, researcher raised some recommends to enhance the lecture’s commitment in  non-public  university. Keywords: non-public uinversity, commitment, lecture, job satisfactio

LG-Hand: Advancing 3D Hand Pose Estimation with Locally and Globally Kinematic Knowledge

3D hand pose estimation from RGB images suffers from the difficulty of obtaining the depth information. Therefore, a great deal of attention has been spent on estimating 3D hand pose from 2D hand joints. In this paper, we leverage the advantage of spatial-temporal Graph Convolutional Neural Networks and propose LG-Hand, a powerful method for 3D hand pose estimation. Our method incorporates both spatial and temporal dependencies into a single process. We argue that kinematic information plays an important role, contributing to the performance of 3D hand pose estimation. We thereby introduce two new objective functions, Angle and Direction loss, to take the hand structure into account. While Angle loss covers locally kinematic information, Direction loss handles globally kinematic one. Our LG-Hand achieves promising results on the First-Person Hand Action Benchmark (FPHAB) dataset. We also perform an ablation study to show the efficacy of the two proposed objective functions

Identification and sequence analysis of a dreb subfamily transcription factor involved in drought stress tolerance from rice

DRE (dehydration responsive element)/CRT (C-repeat) is a cis-acting element that involves in gene expression responsive to abiotic stress in higher plants. To date, all well known DREBP transcription factors in Arabidopsis, rice, maize and other plants regulate gene expression in response to drought, high-salt and cold stresses by binding specifically to DRE/CRT. Using a target sequence of 50 nucleotides on Glutamate dehydrogenase-like protein (JRC2606) promoter containing the core sequence of DRE cis-acting element (A/GCCGAC) for yeast one-hybrid screening, we have identified two transcription factors:  a completely homology of OsRAP2.4A gene and another is a new sequence. The new sequence contained an ORF (Open Reading Frame) of 1017-bp and 5’ non-coding area of 35-bp and 3’ non-coding area of 341-bp. The deduced amino acid sequence contains an AP2 domain and belongs to  the subgroup  A6  of DREB subfamily, temporarily named OsRAP2.4B. Sequence alignment showed that OsRap2.4B had homology with ZmDBF, a maize transcription factor involved in drought stress tolerance

A DfT Architecture for Asynchronous Networks-on-Chip

International audienceThe Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these network architectures. To test the SoCs, the main challenge is to reach into the embedded cores (i.e, the IPs). In this case, the DFT techniques that integrate test architectures into the SoCs to ease the test of these SoCs are really favoured. In this paper, we present a new methodology for testing NoC architectures. A modular, generic, scalable and configurable DFT architecture is developed in order to ease the test of NoC architectures. The target of this test architecture is asynchronous NoC architectures that are implemented in GALS systems. The proposed architecture is therefore named ANOC-TEST and is implemented in QDI asynchronous circuits. In addition, this architecture can be used to test the computing resources of the networked SoCs. Some initial results and conclusions are also give

How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes

International audienceThe Network-on-Chip (NoC) paradigm is currently known as an alternative solution for the on chip communication in the next SoC generation, especially, asynchronous NoCs. One of the challenges for asynchronous NoC-based systems design is testing asynchronous network architectures for manufacturing defects. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high-speed Test Access Mechanism (TAM). This architecture is designed to test all network elements (routers, communication channels), but it can also be used to test computational resources. In this paper, we introduce how to realize and implement the test wrapper in Quasi Delay Insensitive (QDI) asynchronous logic style. The validation and experimental results are also presented

High-Level Modeling and Simulation of a Novel Reconfigurable Network-on-Chip Router

In this paper, we present a novel router architecture for implementing a Reconfigurable Network-on-Chip (RNoC) at high-level design using SystemC. The RNoC is an adaptive NoC-based system-on-chip providing a dynamic reconfigurable communication mechanism. By adding a virtual port – named Routing Modification port – into the conventional router architecture, the network router is able to route communication data flexibly whenever the target routing path is blocked, by unwanted defects or intently by a software programme to meet the requirements of applications. The proposed architecture has been modeled in SystemC/C++, simulated and verified within a 2D mesh 5×5 network platform. In normal communication mode, the static XY routing algorithm is used while the West-First algorithm with a proposed prohibited router surrounding technique is applied in reconfiguration mode. Experimental results are also reported to compare the performance of the network architecture in different operation modes as well as with other works

2D Parity Product Code for TSV online fault correction and detection

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs).  However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To enhance the reliability of TSV connections, using error correction code to detect and correct faults automatically has been demonstrated as a viable solution.This paper presents a 2D Parity Product Code (2D-PPC) for TSV fault-tolerance with the ability to correct one fault and detect, at least, two faults.  In an implementation of 64-bit data and 81-bit codeword, 2D-PPC can detect over 71 faults, on average. Its encoder and decoder decrease the overall latency by 38.33% when compared to the Single Error Correction Double Error Detection code.  In addition to the high detection rates, the encoder can detect 100% of its gate failures, and the decoder can detect and correct around 40% of its individual gate failures. The squared 2D-PPC could be extended using orthogonal Latin square to support extra bit correction